In coherent communications systems, the carrier phase of the transmitter and the local phase generated by the receiver may differ due to oscillator drift, differences in temperature, and other factors. In such systems, the phase of the receiver is generally synchronized or locked relative to the phase of the transmitter in order to allow the receiver to perform demodulation effectively.
Traditionally, Costas loops, and other Phase Locked Loops (PLL), have been employed to achieve the phase synchronization or lock. However, such loops are generally complex and difficult to implement in a digital communication system. Another potential problem with employing such loops is that the time to achieve phase lock may become excessive. The initial phase error is often large, since the transmitter and the receiver are initially un-synchronized. In some cases, depending upon the particular PLL, synchronization may not be achieved, due to phenomena such as lingering, or terminal loop hang-up.
Aided acquisition of phase lock with PLL has been employed to reduce the time to achieve phase lock. In a representative example of aided acquisition, a voltage ramp, or other external driving signal, may be input to an oscillator of the PLL in order to drive the PLL through a phase space that is suspected to contain the lock-in-region. Such aided acquisition generally achieves phase lock more rapidly than unaided acquisition. However, often there is a lack of a good estimate of the lock-in-region.